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About the Module
A total of 16777216 colors (24 bits) in passive color mode
Up to 8-bit (each) passive dual-scan color displays
Up to 16-bit per pixel for active single-panel color displays
Up to 24-bit per pixel single-panel color smart panels
Support for display sizes from 1x1 to 800x600 pixels
LCD controller contains a 64-entry x 24-bit wide output FIFO that stores
pixel pin data before it is driven out to the pins
Overlays supported with pixel depths of 16, 24 and 25 bpp in RGBT format
Provides one base layer plus two overlays for single-scan displays; maximum
size of each overlay can equal the display size
Hardware support for color-space conversion from YCbCr to RGB for video
streams
Support hardware cursor for single-scan display
Programmable pixel clock from 52.0 MHz to 25.4 kHz
Supports little-endian ordering of pixels in frame buffer
Programmable interrupts for input and output FIFOs (underrun)
The color depth determines the number of pins used. All 16 bpp active displays
require 16 data lines. All 18 bpp active displays require 18 data lines. Only with 24
bpp does the PXA270 processor use a different number of pins than the color depth;
the processor outputs the data on 8 lines.
Note: ConnectCore XP 270 only supports externally a 16-bit LCD data bus. LCD[17]
and LCD[16] aren’t routed on the module’s connector due to place availability
on the connector. That means it’s impossible to implement 18bpp displays
with ConnectCore XP 270.
The next diagram shows the Intel PXA270 LCD Controller Unit. For more information,
see “Intel PXA27x Processor Family Developer’s Manual – Order Number: 280000-002”.
www.digi.com
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DGA-LT10AK1221C
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